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HM-6514
March 1997
1024 x 4 CMOS RAM
Description
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature.
Features
* Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max * Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min * TTL Compatible Input/Output * Common Data Input/Output * Three-State Output * Standard JEDEC Pinout * Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max * 18 Pin Package for High Density * On-Chip Address Register * Gated Inputs - No Pull Up or Pull Down Resistors Required
Ordering Information
120ns HM3-6514S-9 HM1-6514S-9 24502BVA 8102402VA 200ns HM3-6514B-9 HM1-6514B-9 8102404VA 300ns HM3-6514-9 HM1-6514-9 8102406VA HM4-6514-B TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to +125oC PACKAGE PDIP CERDIP JAN# SMD# CLCC PKG. NO. E18.3 F18.3 F18.3 F18.3 J18.B J18.B
Pinouts
HM-6514 (PDIP, CERDIP) TOP VIEW
A6 A5 A4 A3 A0 A1 A2 E GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A7 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ3 10 W
HM-6514 (CLCC) TOP VIEW
A6 VCC 18 A5
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable
A0 5 6 7 A4 A3 3 4
2
1
17 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2
Data Input Data Output
A1 A2
8 E
9 GND
10 W
11 DQ3
A7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2995.1
6-1
HM-6514 Functional Diagram
LSB A9 A8 A7 A6 A5 A4
A LATCHED ADDRESS REGISTER 6 A 6 L G L 16 16 16 16 GATED COLUMN I/O SELECT G GATED ROW DECODER 64 x 64 MATRIX
64
LSB A2 A1 A0 A3
A LATCHED ADDRESS REGISTER 4 A 4 4 1 OF 4
E W DQ
6-2
HM-6514
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W N/A CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W 33oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Ranges: HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40oC to +85oC HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9) TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) LIMITS
SYMBOL ICCSB
PARAMETER Standby Supply Current HM-6514-9 HM-6514-8
MIN -
MAX 25 50 7
UNITS A A mA A A V A A V V V V V
TEST CONDITIONS IO = 0mA, E = VCC -0.3V, VCC = 5.5V
ICCOP
Operating Supply Current (Note 1)
E = 1MHz, IO = 0mA, VI = GND, VCC = 5.5V IO = 0mA, VCC = 2.0V, E = VCC
ICCDR
Data Retention Supply Current
HM-6514-9 HM-6514-8
2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 VCC -0.4
15 25 +1.0 +1.0 0.8 VCC +0.3 0.4 -
VCCDR II IIOZ VIL VIH VOL VOH1 VOH2
Data Retention Supply Voltage Input Leakage Current Input/Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Input/Output Capacitance (Note 2)
VI = VCC or GND, VCC = 5.5V VIO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 2.0mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100A, VCC = 4.5V
Capacitance
SYMBOL CI CIO NOTES:
MAX 8 10
UNITS pF pF
TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes.
6-3
HM-6514
AC Electrical Specifications
VCC = 5V 10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9) TA = -55oC to +125oC (HM-6514B-8, HM-6514-8) LIMITS HM-6514S-9 SYMBOL
(1) TELQV (2) TAVQV (3) TELQX
HM-6514B-9 MIN 5 MAX 220 220 -
HM-6514-9 MIN 5 MAX 300 320 UNITS ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3)
PARAMETER Chip Enable Access Time Address Access Time Chip Enable Output Enable Time Chip Enable Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Chip Enable Write Pulse Setup Time Chip Enable Write Pulse Hold Time Data Setup Time Data Hold Time Write Data Delay Time Early Output High-Z Time Late Output High-Z Time Read or Write Cycle Time
MIN 5
MAX 120 120 -
(4) TEHQZ
-
50
-
80
-
100
ns
(Notes 2, 3)
(5) TELEH
120
-
200
-
300
-
ns
(Notes 1, 3)
(6) TEHEL
50
-
90
-
120
-
ns
(Notes 1, 3)
(7) TAVEL (8) TELAX (9) TWLWH (10) TWLEH
0 40 120 120
-
20 50 200 200
-
20 50 300 300
-
ns ns ns ns
(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
(11) TELWH
120
-
200
-
300
-
ns
(Notes 1, 3)
(12) TDVWH (13) TWHDX (14) TWLDV (15) TWLEL (16) TEHWH (17) TELEL
50 0 70 0 0 170
-
120 0 80 0 0 290
-
200 0 100 0 0 420
-
ns ns ns ns ns -
(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)
NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL.
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HM-6514 Timing Waveforms
(2) TAVQV (7) TAVEL A (6) TEHEL E (1) TELQV DQ W TIME REFERENCE -1 0 1 2 3 4 5 HIGH Z (3) TELQX (4) TEHQZ VALID DATA OUT HIGH Z (8) TELAX VALID ADD (2) TAVQY (5) TELEH (17) TELEL (7) TAVEL NEXT ADD (6) TEHEL
FIGURE 1. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H W X H H H H X H A X V X X X X V DATA I/O DQ Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Read Accomplished Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes
enabled, but data is not valid until during time (T = 2). W must remain high throughout the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all inputs, and ready the RAM for the next memory cycle (T = 4).
6-5
HM-6514 Timing Waveforms (Continued)
TELAX TAVEL A VALID ADD TELEL TEHEL E TWLEH TELWL TWLWH W HIGH Z DQ TWLDV VALID DATA INPUT TDVWH TELWH TIME REFERENCE -1 0 1 2 3 4 5 TWHDZ HIGH Z TWHEH TELEH TEHEL TEVAL NEXT ADD
FIGURE 2. WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L H X X E H W X X L A X V X X X X V DQ Z Z Z V Z Z Z Memory Disabled Cycle Begins, Addresses are Latched Write Period Begins Data In is Written Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION
The write cycle is initiated by the falling edge of E (T = 0), which latches the address information in the on-chip registers. There are two basic types of write cycles, which differ in the control of the common data-in/data-out bus. Case 1: E falls before W falls The output buffers may become enabled (reading) if E falls before W falls. W is used to disable (three-state) the outputs so input data can be applied. TWLDV must be met to allow the W signal time to disable the outputs before applying input data. Also, at the end of the cycle the outputs may become active if W rises before E. The RAM outputs and all inputs will three-state after E rises (TEHQZ). In this type of write cycle TWLEL and TEHWH may be ignored. Case 2: E falls equal to or after W falls, and E rises before or equal to W rising
This E and W control timing will guarantee that the data outputs will stay disabled throughout the cycle, thus, simplifying the data input timing. TWLEL and TEHWH must be met, but TWLDV becomes meaningless and can be ignored. In this cycle TDVWH and TWHDX become TDVEH and TEHDX. In other words, reference data setup and hold times to the E rising edge.
IF Case 1 Case 2 E falls before W E falls after W and E rises before W OBSERVE TWLDV TWLEL TEHWH IGNORE TWLEL TWLDV TWHDX
If a series of consecutive write cycles are to be performed, W may be held low until all desired locations have been written (an extension of Case 2).
6-6
HM-6514 Test Load Circuit
DUT (NOTE 1) CL
IOH
+ -
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE: 1. Test head capacitance.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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